VDAT 2018
Thiagarajar College of Engineering
June 28th- June 30th 2018


Researchers , academicians and professionals are invited to submit papers in the following topics (but not limited to)

Download Call for Papers

Device modeling and Simulation.

Advanced CMOS Devices

Emerging memory devices

Reliability Physics, Characterization and test

Multi-gate/ FDSOI device-circuit interaction.

Logic and behavioural synthesis.

Placement, routing and floor Planning.

CAD tools.

Design Automation.


Organic Electronic


2-D material for electronic devices.

Device physics design and circuits using non- silicon materials

CMOS Analog, Mixed-Signal and digital circuits.

Circuit timing and Power models.

Low Power and near/sub threshold circuit design

Analog, Mixed-Signal and digital system design.

Reconfigurable logic/computation.

Design For Manufacturability.

Design Verification, Test, Reliability and Fault Tolerance

Formal Verification


Fault Modeling

Post-silicon Validation

Testing memories and regular logic arrays.

Design for manufacturability and yield analysis.


Soft copies of papers should be submitted as a .pdf file as per the IEEE conference paper format submits not exceeding six A4 size pages. And soft copy of the paper should be uploaded on the symposium web site. After the completion of Plagiarism checking process, Received papers will be assigned to reviewers.

There will be double blind review of the paper. Therefore do not include authors' name in the submitted paper. A Paper with authors' name will not be considered for review. The write-up should also not disclose the identity of the authors. The paper must include an abstract of about 250 words and maximum of five keywords related to the topic of the paper. The acceptance of the paper is based on the following factors: The purpose of the work; The manner and degree to which it advances the art; Specific new results that have been obtained and their significance.