VDAT 2018
Thiagarajar College of Engineering
June 28th- June 30th 2018


Researchers, academicians and professionals are invited to present full day (6 hrs) or half day (3 hrs) tutorials at VDAT-2018

Circuit and Device Interaction.

Emerging Devices and Technologies.

Digital, Analog / Mixed Signal circuit Design.

VLSI Technology.



Modeling and Simulation of Devices, Circuit and Systems.

Sensor / MEMS.


Organic Electronics.

VLSI System Level Design VLSI Architecture.

Title of the tutorial :

The title will appear in the symposium program if the proposal is accepted.

Abstract of the tutorial :

This abstract will be used to advertise the proposal, for instance, on the symposium’s web site prior to the symposium. The abstract should be 250 words long at the most.

Proposed duration :

Half-day tutorials will run for a total of about 3 hours; full day tutorials will run for about 6 hours.

Prerequisite knowledge :

What the attendees should already know.

Detailed outline :

The topics covered in the tutorial will be listed and briefly discussed in the outline, along with the amount of time planned for each topic. This should be limited to 2500 words.

Tutorial goals :

This is a short message on the tutorial’s goals and benefits to prospective participants.

Background information of the presenter(s) should be limited to 1-2 pages and contain Names, affiliations, homepages and contact details. Short biographies including related recent publication. Information about previous tutorials given by the same presenters (title, location, number of attendees, etc.).

Tutorials for Presentation

Please make sure to indicate the tutorial you will attend during registration.

Taking Reuse to Next Level: Exploiting Transaction Level Modeling (TLM) for Universal Verification Methodology (UVM).

- Download Abstract & Bio

Speaker :

Nishit Gupta, Scientist C, Microelectronics Development Division, R&D in Electronics Group, Ministry of Electronics & Information Technology, Government of India, New Delhi.

Date & Time :

28.6.18 , 9:30AM- 12:30PM

Recent Trends in Modeling and Simulation of Defects in Analog Circuits and their Applications.

- Download Abstract & Bio

Speaker :

Vijay Kumar Sankaran, Custom IC, Cadence Design Systems(India)Pvt.Ltd.,Bangalore.

Date & Time :

28.6.18 , 9:30AM- 12:30PM

Tunnel Field Effect Transistors and Re-configurable Device: A New Paradigm in Emerging Device Technology

- Download Abstract & Bio

Speaker :

Sudeb. Dasgupta, Associate Professor in Microelectronics and VLSI Group of the Department of ECE, IIT, Roorkee

Date & Time :

28.6.18 , 2:00PM- 5:00PM

IoT Security: the darker side of the cloud

- Download Abstract & Bio

Speaker :

Yadav Preet, NXP Semiconductors, Noida, India

Date & Time :

28.6.18 , 2:00PM- 5:00PM

Important Note:

* All presenters listed in the tutorial proposal must be available for tutorial presentation.
* Consent should be obtained from all the presenters and all organizations involved in presenting the material and also for travel before making the tutorial proposal.
* The tutorial proposal may be sent to vdat2018@tce.edu
* All material from individual presenters must be combined into a single tutorial presentation, as per the presentation guidelines (to be communicated at the time of acceptance).
* Accepted tutorial abstracts will be published in conference proceedings.